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CSI: Intel’s asymmetric response to HyperTransport success

Intel last week revealed some details of future Itanium processors, in particular regarding the use of high-speed interconnects in high-end server microprocessors starting in 2021. However, the so-called CSI (Common System Interconnect) will appear in both the Itanium lineup and the Xeon processor line.

The first processor to use a CSI connection instead of the traditional front-side bus (FSB) to communicate with external components will be the Itanium quad-core chip, codenamed Tukwila. Planned to debut in 2021, processor expected to deliver twice the performance of the Itanium 9000 series (Montecito).

The new Itanium, whose trial deliveries may begin this year, will also support multithreading – it will process two computational threads per core, completely analogous to the unforgettable HyperThreading technology.

As far as CSI is concerned, Intel is pinning its hopes on the technology to surpass HyperTransport and, according to Jim Fister, technology strategist at Intel’s Digital Enterprise group, with CSI, Intel processors will be able to run much faster than FSB, which has reached 1 , 3 GHz. With CSI, Intel wants to “kill two birds with one stone”: the technology will have to provide coherent data transfer between small groups of local processors, as well as uneven communication of the memory address space between 128 processors in a more distributed system. The latter may require an additional software layer to equalize different memory latency times in different parts of the system. It is reported that Intel is now conducting laboratory tests of the first processors manufactured according to the 45nm process technology. Depending on their success, Intel will reveal further details of the CSI technology, possibly as early as this summer.

After Tukwila, we recall that Intel plans to release Paulson, which will have 6 to 10 cores. For their production, most likely, 65-nm and 45-nm norms will be involved, respectively.

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